Module pml4 

x86-64 Page Map Level 4 (PML4)

This module defines strongly-typed wrappers around the top-level x86-64 page-table layer (PML4):

• L4Index: index type for bits 47..39 of a canonical virtual address.
• Pml4Entry: a single PML4 entry (must not be a large page).
• PageMapLevel4: a 4 KiB-aligned array of 512 PML4 entries.

Background

In 4-level paging, the PML4 selects a Page-Directory-Pointer Table (PDPT). A PML4E must have PS=0 (no large pages at this level). Each entry holds flags and the physical base address of the next-level table. The index is derived from VA bits [47:39].

Guarantees & Invariants

• PageMapLevel4 is 4 KiB-aligned and has exactly 512 entries.
• Pml4Entry::present_with enforces PS=0 for PML4Es.
• Accessors avoid unsafe operations and prefer explicit types such as PhysicalPage<Size4K> for next-level tables.

Structs

L4Index

Index into the PML4 table (derived from virtual-address bits [47:39]).

PageMapLevel4

The top-level page map (PML4).

Pml4Entry

L4 PML4E — pointer to a PDPT (non-leaf; PS must be 0).