Struct Pml4Entry 

#[repr(transparent)]
pub struct Pml4Entry(u64);

L4 PML4E — pointer to a PDPT (non-leaf; PS must be 0).

This entry never maps memory directly. Bits that are meaningful only on leaf entries (e.g., dirty, global) are ignored here.

• Physical address (bits 51:12) is a 4 KiB-aligned PDPT.
• NX participates in permission intersection across the walk.
• PKU may be repurposed as OS-available when not supported.

Reference: AMD APM / Intel SDM paging structures (x86-64).

Tuple Fields

0: u64

Implementations

impl Pml4Entry

const PRESENT_BITS: usize = 1usize

const PRESENT_OFFSET: usize = 0usize

const WRITABLE_BITS: usize = 1usize

const WRITABLE_OFFSET: usize = 1usize

const USER_BITS: usize = 1usize

const USER_OFFSET: usize = 2usize

const WRITE_THROUGH_BITS: usize = 1usize

const WRITE_THROUGH_OFFSET: usize = 3usize

const CACHE_DISABLE_BITS: usize = 1usize

const CACHE_DISABLE_OFFSET: usize = 4usize

const ACCESSED_BITS: usize = 1usize

const ACCESSED_OFFSET: usize = 5usize

const OS_AVAILABLE_LOW_BITS: usize = 3usize

const OS_AVAILABLE_LOW_OFFSET: usize = 9usize

const PHYS_ADDR_51_12_BITS: usize = 40usize

const PHYS_ADDR_51_12_OFFSET: usize = 12usize

const OS_AVAILABLE_HIGH_BITS: usize = 7usize

const OS_AVAILABLE_HIGH_OFFSET: usize = 52usize

const PROTECTION_KEY_BITS: usize = 4usize

const PROTECTION_KEY_OFFSET: usize = 59usize

const NO_EXECUTE_BITS: usize = 1usize

const NO_EXECUTE_OFFSET: usize = 63usize

pub const fn new() -> Self

Creates a new default initialized bitfield.

pub const fn from_bits(bits: u64) -> Self

Convert from bits.

pub const fn into_bits(self) -> u64

Convert into bits.

pub const fn present(&self) -> bool

Present (bit 0): valid entry if set.

When clear, the entry is not present and most other fields are ignored.

Bits: 0..1

pub const fn with_present_checked(self, value: bool) -> Result<Self, ()>

Present (bit 0): valid entry if set.

When clear, the entry is not present and most other fields are ignored.

Bits: 0..1

pub const fn with_present(self, value: bool) -> Self

Present (bit 0): valid entry if set.

When clear, the entry is not present and most other fields are ignored.

Bits: 0..1

pub const fn set_present(&mut self, value: bool)

Present (bit 0): valid entry if set.

When clear, the entry is not present and most other fields are ignored.

Bits: 0..1

pub const fn set_present_checked(&mut self, value: bool) -> Result<(), ()>

Present (bit 0): valid entry if set.

When clear, the entry is not present and most other fields are ignored.

Bits: 0..1

pub const fn writable(&self) -> bool

Writable (bit 1): write permission.

Intersects with lower-level permissions; supervisor write protection, SMEP/SMAP, CR0.WP, and U/S checks apply.

Bits: 1..2

pub const fn with_writable_checked(self, value: bool) -> Result<Self, ()>

Writable (bit 1): write permission.

Intersects with lower-level permissions; supervisor write protection, SMEP/SMAP, CR0.WP, and U/S checks apply.

Bits: 1..2

pub const fn with_writable(self, value: bool) -> Self

Writable (bit 1): write permission.

Intersects with lower-level permissions; supervisor write protection, SMEP/SMAP, CR0.WP, and U/S checks apply.

Bits: 1..2

pub const fn set_writable(&mut self, value: bool)

Writable (bit 1): write permission.

Intersects with lower-level permissions; supervisor write protection, SMEP/SMAP, CR0.WP, and U/S checks apply.

Bits: 1..2

pub const fn set_writable_checked(&mut self, value: bool) -> Result<(), ()>

Writable (bit 1): write permission.

Intersects with lower-level permissions; supervisor write protection, SMEP/SMAP, CR0.WP, and U/S checks apply.

Bits: 1..2

pub const fn user(&self) -> bool

User/Supervisor (bit 2): allow user-mode access if set.

If clear, access is restricted to supervisor (ring 0).

Bits: 2..3

pub const fn with_user_checked(self, value: bool) -> Result<Self, ()>

User/Supervisor (bit 2): allow user-mode access if set.

If clear, access is restricted to supervisor (ring 0).

Bits: 2..3

pub const fn with_user(self, value: bool) -> Self

User/Supervisor (bit 2): allow user-mode access if set.

If clear, access is restricted to supervisor (ring 0).

Bits: 2..3

pub const fn set_user(&mut self, value: bool)

User/Supervisor (bit 2): allow user-mode access if set.

If clear, access is restricted to supervisor (ring 0).

Bits: 2..3

pub const fn set_user_checked(&mut self, value: bool) -> Result<(), ()>

User/Supervisor (bit 2): allow user-mode access if set.

If clear, access is restricted to supervisor (ring 0).

Bits: 2..3

pub const fn write_through(&self) -> bool

Page Write-Through (PWT, bit 3): write-through caching policy.

Effective only if caching isn’t disabled for the mapping.

Bits: 3..4

pub const fn with_write_through_checked(self, value: bool) -> Result<Self, ()>

Page Write-Through (PWT, bit 3): write-through caching policy.

Effective only if caching isn’t disabled for the mapping.

Bits: 3..4

pub const fn with_write_through(self, value: bool) -> Self

Page Write-Through (PWT, bit 3): write-through caching policy.

Effective only if caching isn’t disabled for the mapping.

Bits: 3..4

pub const fn set_write_through(&mut self, value: bool)

Page Write-Through (PWT, bit 3): write-through caching policy.

Effective only if caching isn’t disabled for the mapping.

Bits: 3..4

pub const fn set_write_through_checked(&mut self, value: bool) -> Result<(), ()>

Page Write-Through (PWT, bit 3): write-through caching policy.

Effective only if caching isn’t disabled for the mapping.

Bits: 3..4

pub const fn cache_disable(&self) -> bool

Page Cache Disable (PCD, bit 4): disable caching if set.

Strongly impacts performance; use for MMIO or compliance with device requirements. Effective policy is the intersection across the walk.

Bits: 4..5

pub const fn with_cache_disable_checked(self, value: bool) -> Result<Self, ()>

Page Cache Disable (PCD, bit 4): disable caching if set.

Strongly impacts performance; use for MMIO or compliance with device requirements. Effective policy is the intersection across the walk.

Bits: 4..5

pub const fn with_cache_disable(self, value: bool) -> Self

Page Cache Disable (PCD, bit 4): disable caching if set.

Strongly impacts performance; use for MMIO or compliance with device requirements. Effective policy is the intersection across the walk.

Bits: 4..5

pub const fn set_cache_disable(&mut self, value: bool)

Page Cache Disable (PCD, bit 4): disable caching if set.

Strongly impacts performance; use for MMIO or compliance with device requirements. Effective policy is the intersection across the walk.

Bits: 4..5

pub const fn set_cache_disable_checked(&mut self, value: bool) -> Result<(), ()>

Page Cache Disable (PCD, bit 4): disable caching if set.

Strongly impacts performance; use for MMIO or compliance with device requirements. Effective policy is the intersection across the walk.

Bits: 4..5

pub const fn accessed(&self) -> bool

Accessed (A, bit 5): set by CPU on first access via this entry.

Software may clear to track usage; not a permission bit.

Bits: 5..6

pub const fn with_accessed_checked(self, value: bool) -> Result<Self, ()>

Accessed (A, bit 5): set by CPU on first access via this entry.

Software may clear to track usage; not a permission bit.

Bits: 5..6

pub const fn with_accessed(self, value: bool) -> Self

Accessed (A, bit 5): set by CPU on first access via this entry.

Software may clear to track usage; not a permission bit.

Bits: 5..6

pub const fn set_accessed(&mut self, value: bool)

Accessed (A, bit 5): set by CPU on first access via this entry.

Software may clear to track usage; not a permission bit.

Bits: 5..6

pub const fn set_accessed_checked(&mut self, value: bool) -> Result<(), ()>

Accessed (A, bit 5): set by CPU on first access via this entry.

Software may clear to track usage; not a permission bit.

Bits: 5..6

pub const fn os_available_low(&self) -> u8

OS-available low (bits 9..11): not interpreted by hardware.

Bits: 9..12

pub const fn with_os_available_low_checked(self, value: u8) -> Result<Self, ()>

OS-available low (bits 9..11): not interpreted by hardware.

Bits: 9..12

pub const fn with_os_available_low(self, value: u8) -> Self

OS-available low (bits 9..11): not interpreted by hardware.

Bits: 9..12

pub const fn set_os_available_low(&mut self, value: u8)

OS-available low (bits 9..11): not interpreted by hardware.

Bits: 9..12

pub const fn set_os_available_low_checked( &mut self, value: u8, ) -> Result<(), ()>

OS-available low (bits 9..11): not interpreted by hardware.

Bits: 9..12

const fn phys_addr_51_12(&self) -> u64

Next-level table physical address (bits 12..51).

Stores the PDPT base (4 KiB-aligned). The low 12 bits are omitted.

Bits: 12..52

const fn with_phys_addr_51_12_checked(self, value: u64) -> Result<Self, ()>

Next-level table physical address (bits 12..51).

Stores the PDPT base (4 KiB-aligned). The low 12 bits are omitted.

Bits: 12..52

const fn with_phys_addr_51_12(self, value: u64) -> Self

Next-level table physical address (bits 12..51).

Stores the PDPT base (4 KiB-aligned). The low 12 bits are omitted.

Bits: 12..52

const fn set_phys_addr_51_12(&mut self, value: u64)

Next-level table physical address (bits 12..51).

Stores the PDPT base (4 KiB-aligned). The low 12 bits are omitted.

Bits: 12..52

const fn set_phys_addr_51_12_checked(&mut self, value: u64) -> Result<(), ()>

Next-level table physical address (bits 12..51).

Stores the PDPT base (4 KiB-aligned). The low 12 bits are omitted.

Bits: 12..52

pub const fn os_available_high(&self) -> u8

OS-available high (bits 52..58): not interpreted by hardware.

Bits: 52..59

pub const fn with_os_available_high_checked(self, value: u8) -> Result<Self, ()>

OS-available high (bits 52..58): not interpreted by hardware.

Bits: 52..59

pub const fn with_os_available_high(self, value: u8) -> Self

OS-available high (bits 52..58): not interpreted by hardware.

Bits: 52..59

pub const fn set_os_available_high(&mut self, value: u8)

OS-available high (bits 52..58): not interpreted by hardware.

Bits: 52..59

pub const fn set_os_available_high_checked( &mut self, value: u8, ) -> Result<(), ()>

OS-available high (bits 52..58): not interpreted by hardware.

Bits: 52..59

pub const fn protection_key(&self) -> u8

Protection Key / OS use (bits 59..62).

If PKU is supported and enabled, these bits select the protection key; otherwise they may be used by the OS.

Bits: 59..63

pub const fn with_protection_key_checked(self, value: u8) -> Result<Self, ()>

Protection Key / OS use (bits 59..62).

If PKU is supported and enabled, these bits select the protection key; otherwise they may be used by the OS.

Bits: 59..63

pub const fn with_protection_key(self, value: u8) -> Self

Protection Key / OS use (bits 59..62).

If PKU is supported and enabled, these bits select the protection key; otherwise they may be used by the OS.

Bits: 59..63

pub const fn set_protection_key(&mut self, value: u8)

Protection Key / OS use (bits 59..62).

If PKU is supported and enabled, these bits select the protection key; otherwise they may be used by the OS.

Bits: 59..63

pub const fn set_protection_key_checked(&mut self, value: u8) -> Result<(), ()>

Protection Key / OS use (bits 59..62).

If PKU is supported and enabled, these bits select the protection key; otherwise they may be used by the OS.

Bits: 59..63

pub const fn no_execute(&self) -> bool

No-Execute (NX, bit 63 / XD on Intel).

When set and EFER.NXE is enabled, instruction fetch is disallowed through this entry (permission intersection applies).

Bits: 63..64

pub const fn with_no_execute_checked(self, value: bool) -> Result<Self, ()>

No-Execute (NX, bit 63 / XD on Intel).

When set and EFER.NXE is enabled, instruction fetch is disallowed through this entry (permission intersection applies).

Bits: 63..64

pub const fn with_no_execute(self, value: bool) -> Self

No-Execute (NX, bit 63 / XD on Intel).

When set and EFER.NXE is enabled, instruction fetch is disallowed through this entry (permission intersection applies).

Bits: 63..64

pub const fn set_no_execute(&mut self, value: bool)

No-Execute (NX, bit 63 / XD on Intel).

When set and EFER.NXE is enabled, instruction fetch is disallowed through this entry (permission intersection applies).

Bits: 63..64

pub const fn set_no_execute_checked(&mut self, value: bool) -> Result<(), ()>

No-Execute (NX, bit 63 / XD on Intel).

When set and EFER.NXE is enabled, instruction fetch is disallowed through this entry (permission intersection applies).

Bits: 63..64

impl Pml4Entry

pub const fn zero() -> Self

Create a zero (non-present) entry with all bits cleared.

pub const fn next_table(self) -> Option<PhysicalPage<Size4K>>

If present, return the physical page of the next-level PDPT.

Returns None if the entry is not present. The returned page is always 4 KiB-aligned as required for page-table bases.

pub const fn present_with( flags: VirtualMemoryPageBits, next_pdpt_page: PhysicalPage<Size4K>, ) -> Self

Build a PML4 entry that points to the given PDPT page and applies the provided flags.

Requirements

• flags.large_page() must be false (PS=0). Enforced via debug_assert!.
• This function sets present=1 and the physical base to next_pdpt_page.base().

pub const fn with_physical_address(self, phys: PhysicalPage<Size4K>) -> Self

Set the PDPT base address (must be 4 KiB-aligned).

pub const fn set_physical_address(&mut self, phys: PhysicalPage<Size4K>)

Set the PDPT base address (must be 4 KiB-aligned).

pub const fn physical_address(self) -> PhysicalPage<Size4K>

Get the PDPT base address (4 KiB-aligned).

Trait Implementations

impl Clone for Pml4Entry

fn clone(&self) -> Pml4Entry

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Pml4Entry

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Pml4Entry

fn default() -> Self

Returns the “default value” for a type.

impl From<Pml4Entry> for VirtualMemoryPageBits

fn from(e: Pml4Entry) -> Self

Converts to this type from the input type.

impl From<Pml4Entry> for u64

fn from(v: Pml4Entry) -> u64

Converts to this type from the input type.

impl From<u64> for Pml4Entry

fn from(v: u64) -> Self

Converts to this type from the input type.

impl Copy for Pml4Entry